Process RD Fujitsu turns to SuVolta to halve Cortex-A0 power consumption

Process RD Fujitsu turns to SuVolta to halve Cortex-A0 power consumption

2013/07/24

Deeply depleted channel (DDC) transistors have enabled Fujitsu to halve the power consumption of a 65nm ARM Cortex-M0 core.

The technology, licenced from SuVolta, reduces process variations by removing dopant atoms from the channel, without resorting to finfets or SoI wafers.

Without dopant-derived transistor threshold variations, all the devices on a particular chip are better matched in leakage and speed – so there is less need to over-volt most of the transistors to allow the slowest one to meet its timing constraints.

Fujitsu made the Cortex-A0s on multiple 65nm wafers, using its standard process as a baseline alongside DDC, using split lots (slow, medium and fast wafers) to gather statistical information.

“The baseline needed 1.2V to run at 350MHz, that’s 8mW. The DDC version worked at 350MHz at 4mW, 0.9V,” SuVolta design director David Kidd told Electronics Weekly. “That is with the same GDSK, and essentially the same set of masks: there were some differences in the poly masks.”

The price paid for DDC is a re-ordering of mask use, and an additional epitaxy stage.

“The epi has a very clean interface and has very good uniformity. It is not a source of problems,” said Kidd. “Generally our technology is mask-neutral. You might need to add one or subtract one.”

Other figures claimed for the DDC version of the experimental Cortex-M0 are 35% increased operational speed at 8mW (at 1.1V), and 55% extra speed at 1.2V (11mW).

Body biasing can pull in most corner variation (see graph).

“Body biasing would be done automatically by on-chip bias generator, so from the user point of view, they only need to apply 0.9V,” said Kidd.

Looking purely at on-chip SRAM, again on the 65nm reference process, Kidd is claiming a 150mV reduction Vcc required to retain data at high temperature (see graph).

“SRAM tends to be the first component that fails when reducing supply voltage,” he said. “Power is down 87% in retention mode. That is a substantial way to what you would get if you just shut the RAM down, which is about 95% down.”

The ARM processor was used to evaluate the DDC process at 65nm. DDC production at Fujitsu will be at 55nm. “Fujitsu is sampling now the chip they actually want to put into production later this year,” said Kidd, who would not reveal what the production chip will be.”

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